GIEn=0, Fn=0, TIEn=0, GIRn=0, BRSTH=0, CLKE=0, BBOOT=00, NMI=0, MUR=0, RIEn=0
Control Register
| Fn | For n = {0, 1, 2} Processor A/B to Processor B/A Flag n 0 (0): Clears the Fn bit in the SR register. 1 (1): Sets the Fn bit in the SR register. |
| NMI | Processor B/A Non-maskable Interrupt 0 (0): Non-maskable interrupt is not issued to the Processor B/A by the Processor A/B (default). 1 (1): Non-maskable interrupt is issued to the Processor B/A by the Processor A/B. |
| MUR | Processor A MU Reset 0 (0): N/A. Self clearing bit (default). 1 (1): Asserts the Processor A MU reset. |
| BRSTH | Processor B Reset Hold 0 (0): Release Processor B from reset 1 (1): Hold Processor B in reset |
| CLKE | Processor B/A clock enable 0 (0): Processor B/A platform clock gated when Processor B/A enters a stop mode. 1 (1): Processor B/A platform clock kept running after Processor B/A enters a stop mode, until Processor A/B also enters a stop mode. |
| BBOOT | Processor B Boot Config. 0 (00): Boot from 0x0 1 (01): Boot from DMEM Base 2 (10): Boot from IMEM Base |
| GIRn | For n = {0, 1, 2, 3} Processor A/B General Purpose Interrupt Request n 0 (0): Processor A/B General Interrupt n is not requested to the Processor B/A (default). 1 (1): Processor A/B General Interrupt n is requested to the Processor B/A. |
| TIEn | For n = {0, 1, 2, 3} Processor A/B Transmit Interrupt Enable n 0 (0): Disables Processor A/B Transmit Interrupt n. (default) 1 (1): Enables Processor A/B Transmit Interrupt n. |
| RIEn | For n = {0, 1, 2, 3} Processor A/B Receive Interrupt Enable n 0 (0): Disables Processor A/B Receive Interrupt n. (default) 1 (1): Enables Processor A/B Receive Interrupt n. |
| GIEn | For n = {0, 1, 2, 3} Processor A/B General Purpose Interrupt Enable n 0 (0): Disables Processor A/B General Interrupt n. (default) 1 (1): Enables Processor A/B General Interrupt n. |